Dimensional Scaling of Material Functional Properties to meet Back-End-of-Line (BEOL) Challenges
Dimensional scaling of materials dramatically modifies their electrical, thermal, mechanical, and magnetic properties, as well as their material-property relationship, which in turn alters the physical behavior of nanoscale electronic devices. While low-dimensional nanomaterials could offer interesting functional properties that are size and shape dependent and thus not found in their bulk counterparts, there are also significant challenges related to understanding and controlling material properties at the nanoscale and integration of nanomaterials into hybrid systems at advanced technology nodes. In the case of CMOS electronics, dimensional scaling of feature sizes on the chip offered decades of performance gains in digital computing. However, to further push CMOS scaling in the presence of severe short-channel effects will require new approaches of material and device design with improved performance over conventional approaches. Meanwhile, the scaling of current CMOS interconnects is facing critical roadblocks as a result of enhanced resistivity at scaled technology nodes with smaller cross-sectional dimensions. Hence, the delay and energy costs of data communication between computational units and memory has become a key challenge in current information processing systems. Discovering new materials with weaker scaling laws or completely different conduction mechanisms for interconnects and new concepts of CMOS-compatible non-volatile memory offer interesting alternatives. Yet, to meet the computing needs with radically new interconnect and memory approaches will need advances in theory and modeling, material synthesis, nanodevice fabrication and characterization of electronic, phononic and photonic interactions across many length scales, ranging from the material level to the device and module levels.
Topics covered include, but are not limited to:
- Promising nanoscale conductor materials for local-level on-chip interconnects
- Extreme dielectric materials and processes for local-level on-chip interconnects
- Multi-physics modeling approaches toward designing electrically controlled nanomaterials
- Back-end-of -line (BEOL) optimization, device physics reliability and-circuit benchmarking
- Scalable III-V devices on silicon for optical and terahertz interconnects
- Two-dimensional nanoelectronic and nanophotonic devices and interconnects
- Design of new nanomaterial hybrid structures for beyond-CMOS computing
Guest Editors
Shaloo Rakheja, University of Illinois Urbana-Champaign
Zhihong Chen, Purdue University
Ching-Tzu Chen, IBM